That removes a whopping 100ms delay for the first CPU of a The actual solution comes in several partsġ) General cleanups (init annotations, kernel doc.)Īvoid pointless delay calibration when TSC is synchronized across Large enough the first AP is already waiting when the boot CPU finished the Reduced to waiting for the first AP to report alive or if the system is That's more than 80% of the actual onlining procedure.īy splitting the actual bringup mechanism into two parts this can be On current mainline about 800ms busy waiting for the APs to come up andĪpply microcode. On a two socket SKL server with 56 cores (112 threads) the boot CPU spends To take up to ~8ms on the primary threads depending on the microcode #4 The atomic bringup does the microcode update. Vendor and CPU type, BIOS microcode size etc. Has been measured in the range between 350us and 3.5ms depending on #3 The time for an AP to report alive state in start_secondary() on x86 INIT/SIPI on x86)Ĥ) Let the AP continue through the atomic bringupĥ) Let the AP run the threaded bringup to full online state The current fully serialized bringup does the following per AP:ġ) Prepare callbacks (allocate, intialize, create threads)Ģ) Kick the AP alive (e.g. There are obviously other interesting use cases for this The (kexec) reboot time of cloud servers to reduce the downtime of the The reason why people are interested in parallel bringup is to shorten Git:///pub/scm/linux/kernel/git/tglx/devel.git hotplug Git:///pub/scm/linux/kernel/git/tip/tip x86/apic The early versions of parallel bringup already. Much of that had been pointed out 2 years ago in the discussions about Mostly in the core code and not made an architecture specific tinker Mechanisms and without generalizing it so that the control logic is The existing code without a deeper analysis of the synchronization Synchronization between the core siblings.Ģ) The general design issues discussed in previous parallel bringup patches just glued this mechanism into Synchronization point w/o doing any further x86 specific This ensures that the APs can load microcode before reaching the alive Loading microcode on the siblings is a NOOP on IntelĪnd on AMD it is guaranteed to only modify thread local state. The solution for this is to bringup the primary threads first and after Assume the followingĬPU1.1 makes a decision on $A and $B which might be inconsistent due Vendor independent software correctness issue. This is required by hardware/firmware on Intel. Quiescent state either looping in a place which is aware of potentialĬhanges by the microcode update (see late loading) or in fully quiescent This is a complete rework of the parallel bringup patch series address the issues which were discovered in review:ġ) The X86 microcode loader serialization loading on HT enabled X86 CPUs requires that the microcode is Palmer Dabbelt, linux-riscv, Mark Rutland, Sabin Rapan Bottomley, Helge Deller, linux-parisc, Paul Walmsley, Guo Ren, linux-csky, Thomas Bogendoerfer, linux-mips, Juergen Gross, Boris Ostrovsky, xen-devel, Russell King,Īrnd Bergmann, linux-arm-kernel, Catalin Marinas, Will Deacon, Piccoli, Piotr Gorski, David Woodhouse, Usama Arif, Sean Christopherson, Oleksandr Natalenko, Paul Menzel, ` (40 more replies) 0 siblings, 41 replies 77+ messages in threadįrom: Thomas Gleixner 23:44 UTC ( / raw)Ĭc: x86, David Woodhouse, Andrew Cooper, Brian Gerst,Īrjan van de Veen, Paolo Bonzini, Paul McKenney, Tom Lendacky, 23:44 ` x86/smpboot: Cleanup topology_phys_to_logical_pkg()/die() Thomas Gleixner Cpu/hotplug, x86: Reworked parallel CPU bringup archive mirror help / color / mirror / Atom feed * cpu/hotplug, x86: Reworked parallel CPU bringup 23:44 Thomas Gleixner
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